Position: Design Verification
Engineer (SoC, SystemVerilog /UVM)
Location: Serillingampalli ,
Hyderabad
Job
Description:
We are seeking a talented and
motivated Design Verification Engineer to join our hardware development
team. You will be responsible for verifying complex SoC designs using
industry-standard methodologies such as SystemVerilog and UVM
(Universal Verification Methodology) . The ideal candidate will have a solid
background in digital design verification, strong problem-solving skills, and
hands-on experience with SoC architectures.
Key
Responsibilities:
Required
Skills and Experience:
Thanks and Regards
Sakshee Khampariya
9201975264
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